A high input impedance, a low output impedance and wide output current and output voltage dynamic ranges are some of the desired features for a power amplification circuit.
FIG. 1 is a circuit diagram of a differential operational amplifier known in the prior art. Such an operational amplifier comprises two cascaded amplification stages. An input stage, designated by GM, is formed by a differential transconductance amplifier 10, receiving currents Ip and In, corresponding to input electric potentials Vp and Vn, on two positive and negative inputs, respectively. The transconductance amplifier 10 is connected between two voltage supply terminals, a positive supply terminal 5 and a negative supply terminal 6, respectively, referenced with respect to an electric ground terminal M. Respective electric potentials VCC+ and VCC− of the supply terminals 5 and 6 can, for example, be +2.5 V and −2.5 V. The currents Ip and In are of the order of a few microamps in absolute value. The input electric potentials Vp and Vn can vary between VCC− and VCC+; they form the input signals of the operational amplifier.
The output of the transconductance amplifier 10 forms the output of the input stage. It is connected to a node A that forms an input of the power output stage 100. Capacitors 102 and 103 connect the node A to the supply terminals 5 and 6, respectively. These stabilize the operation of the operational amplifier.
A node D forms an output of the power output stage 100 and is also an output of the operational amplifier. A load 101, of value ZL, is connected between the node D and the ground terminal M. The load 101 is usually equivalent to a resistor connected in parallel with a capacitor (not shown) ZL can, for example, have a modulus equal to 100 ohms.
The power amplification circuit that forms the power output stage 100 is designated in the following description as circuit 100. It comprises two circuit modules 60 and 70. The module 60 comprises two pnp-type bipolar transistors 61 and 62, preferably identical to each other. The emitters of the transistors 61 and 62 are connected to the supply terminal 5 by identical resistors 63 and 64, respectively, with a common value R. R can, for example, be equal to 1 kilo-ohm. The bases of the transistors 61 and 62 are connected to each other, and also to the collector of the transistor 61. In other words, the transistor 61 is configured as a diode. The module 60 thus configured forms a well-known Widlar current source with outflowing currents. This operates as a current mirror: the currents flowing from the collectors of the transistors 61 and 62 are equal to each other.
The module 70 is also a Widlar current source, but with inflowing currents. It has a complementary structure to that of the module 60. The module 70 thus comprises two npn-type bipolar transistors 71 and 72, preferably identical to each other. Each of these transistors has an emitter connected to the supply terminal 6 by a resistor 73 and 74, respectively. The resistors 73 and 74 have the same common value, which can also be the value R, but not necessarily. The respective bases of the transistors 71 and 72 are connected to each other and, in addition, to the collector of the transistor 71.
A current source 7 is connected between the collectors of the transistors 61 and 71. The positive terminal of the source 7 is connected to the collector of the transistor 71, and the negative terminal of the source 7 is connected to the collector of the transistor 61. The intensity I of the current delivered by the source 7 may, for example, be 200 microamps.
The circuit 100 also comprises a module 20 of the ‘push-pull’ type. The module 20 comprises two intermediate bipolar transistors 1 and 2, pnp and npn respectively. The transistors 1 and 2 are preferably matched, in other words they have identical structures but have electrical doping types that are reversed with respect to each other. The bases of the transistors 1 and 2 are connected to each other and to the node A. The emitters of the transistors 1 and 2 are respectively connected to the collectors of the transistors 62 and 72, at a node B and at a node C, respectively. Output transistors 3 and 4, of npn and pnp type respectively, and preferably matched, have their bases connected, respectively, to the nodes B and C. The emitters of the transistors 3 and 4 are connected to each other and to the node D. The collectors of the transistors 3 and 4 are connected to the supply terminals 5 and 6, respectively.
According to the known configuration of the circuit 100, the collector of the intermediate transistor 1 is directly connected to the supply terminal 6, and the collector of the intermediate transistor 2 is directly connected to the supply terminal 5.
When the difference Vp−Vn between the input electric potentials Vp and Vn is positive and progressively increasing, the electric potential of the node A, denoted VA, is also positive and varies according to an amplification characteristic of the transconductance amplifier 10. In practice, VA is equal to a saturation value that depends on VCC+. According to the known operation of the module 20, the transistor 1 is then in an off state. According to the operation in current mirror mode of the module 60, a current equal to I flows between the emitter and the collector of the transistor 62. Consequently, a current I flows from the node B towards the base of the transistor 3. Therefore:i3=β3×I,  (1)
where i3 is the current flowing through the transistor 3 from the collector to the emitter of the latter, and where □3 is the current gain of the transistor 3.
The output current of the circuit 100, denoted iOUT, is then equal to i3−i4, where i4 is the current flowing through the transistor 4, from the emitter to the collector. The orientations of i3 and i4 are indicated in FIG. 1. i3 and i4 are positive. The value of iOUT is limited by the value of i3 given by equation (1). This value is frequently denoted by ISOURCE. It is reached when the input electric potential Vp is higher than the input electric potential Vn, and when the value of the impedance 101 is sufficiently low.
Symmetrically, when the input electric potential Vp is lower than the input electric potential Vn, the electric potential of the node A is negative. The current iOUT is then negative and limited, in absolute value, by the value of i4 given by the equation (2):i4=β4×I,  (2)
where β4 is the current gain of the transistor 4. This value is frequently denoted by ISINK. ISINK thus defined is a positive value.
When the electric potential VA reaches a sufficiently high value, the transistor 62 is in a saturated state. The maximum value that the electric potential VD can reach at the node D is then VCC+−Voh, with:Voh=UBE(3)+UEC sat(62)+R×I,  (3)
where UBE(3) is the difference between the electric potentials of the base and of the emitter of the transistor 3, and where UEC sat(62) is the difference between the electric potentials of the emitter and of the collector of the transistor 62 in the saturated state. Voh is called the drop-out voltage and can reach 1 volt. In the following description, the potential VD is called the output electric potential of the circuit 100.
A drop-out voltage Vol, similar to Voh, limits the value that the potential VD can take when Vp−Vn is negative. The minimum value of VD is then VCC−+Vol. The voltage Vol obeys the expression:Vol=UEB(4)+UCE sat(72)+R×I,  (4)
where UEB(4) is the difference between the electric potentials of the emitter and of the base of the transistor 4, and where UCE sat(72) is the difference between the electric potentials of the collector and of the emitter of the transistor 72 in the saturated state. Vol can also reach 1 volt.
Furthermore, the respective emitters and bases of the transistors 1 to 4 form a closed loop. The difference between the electric potentials VA and VD is therefore given by the following double equation:VA−VD=UBE(1)+UBE(3)=UBE(2)+UBE(4),  (5)
where UBE(j) denotes the electric potential between the base and the emitter of the transistor j, for j=1, 2, 3 or 4.
In the idle state of the circuit 100, in other words when Vp=Vn, no current flows out of the node D in the direction of the impedance 101 (iOUT=0), and the electric potentials of the nodes A and D are equal to each other. The currents flowing, respectively, between the node B and the base of the transistor 3, and between the node C and the base of the transistor 4 are very low compared to the current I. A current i1 equal to I therefore flows in the transistor 1, from the emitter to the collector of the transistor 1. Similarly, a current i2 equal to I flows in the transistor 2, from the collector to the emitter of the transistor 2. It therefore follows from equation (5) that i3=i4=n×I, where n is the ratio of the respective emitter areas of the transistors 3 and 2, or of the transistors 4 and 1:
                    n        =                                            emitter              ⁢                                                          ⁢              area              ⁢                                                          ⁢              of              ⁢                                                          ⁢              transistor              ⁢                                                          ⁢              3                                      emitter              ⁢                                                          ⁢              area              ⁢                                                          ⁢              of              ⁢                                                          ⁢              transistor              ⁢                                                          ⁢              2                                =                                    emitter              ⁢                                                          ⁢              area              ⁢                                                          ⁢              of              ⁢                                                          ⁢              transistor              ⁢                                                          ⁢              4                                      emitter              ⁢                                                          ⁢              area              ⁢                                                          ⁢              of              ⁢                                                          ⁢              transistor              ⁢                                                          ⁢              1                                                          (        6        )            
For example, n can be in the range 1 to 10.
In the idle state of the circuit 100, the total current drawn by the circuit 100, denoted ICONS, is the current flowing between the power supply terminals 5 and 6. It is equal to the sum of the currents flowing respectively in the resistors 63 and 64, of i2 and of i3. Therefore:ICONS=(3+n)×I.  (7)
It is desirable to reduce this value of the total current drawn by a power amplification circuit in the idle state.